MidnightBSD Magus

cad/gplcver

Verilog HDL simulator

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
2.12.a 644 4.1 amd64 gpl2 0 warn pass pass warn Reset Port

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Events

Machine Phase Type Time Message
m4164b fetch info 2026-07-25 07:37:52.868508 Fetch Started
m4164b fetch pass 2026-07-25 07:37:54.369972 Fetch complete.
m4164b build info 2026-07-26 21:08:22.792551 Build Started
m4164b build warn 2026-07-26 21:08:31.538555 MASTER_SITES contains non-HTTPS URLs: http://downloads.sourceforge.net/project/gplcver/gplcver/2.12a/, http://cfhcable.dl.sourceforge.net/project/gplcver/gplcver/2.12a/, http://cytranet.dl.sourceforge.net/project/gplcver/gplcver/2.12a/, http://deac-ams.dl.sourceforge.net/project/gplcver/gplcver/2.12a/, http://deac-fra.dl.sourceforge.net/project/gplcver/gplcver/2.12a/ and 19 more
m4164b build warn 2026-07-26 21:08:31.700578 Build complete.
m4164b scan info 2026-07-28 03:48:05.741063 Scan Started
m4164b scan info 2026-07-28 03:48:22.736376 Virus scan passed.
m4164b scan warn 2026-07-28 03:48:22.777042 YARA found suspicious port shell content.
m4164b scan info 2026-07-28 03:48:23.05179 Source integrity scan passed.
m4164b scan warn 2026-07-28 03:48:23.078256 Scan complete.
m4164b test info 2026-07-28 22:26:43.399302 Test Started
m4164b test pass 2026-07-28 22:26:50.998952 Test complete.

scan Log

== ClamAV package scan ==
/mnt/magus/packages/644/gplcver-2.12.a.mport: OK

== YARA port-file scan ==
/usr/mports/cad/gplcver/Makefile(1): error: syntax error, unexpected identifier
/usr/mports/cad/gplcver/Makefile(16): error: unterminated regular expression

== Source integrity scan ==
Compared cad/gplcver between 70edcb85ec50f0f11f83cbb7af2b1a051439152a and 177ae033a7ad8459e5e20760b547a2b46a0c1e79.
Changed files:
  cad/gplcver/Makefile
No source integrity warnings.

Links

Depends On

Depend Of

Nothing

Categories

CVEs

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LLM Analysis