cad/iverilog
Verilog simulation and synthesis tool
| Flavor | Version | Run | OSVersion | Arch | License | Restricted | Build | Fetch | Test | Scan | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 12.0_1 | 643 | 4.1 | i386 | gpl2 | 0 | pass | pass | pass | warn |
License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept
Events
| Machine | Phase | Type | Time | Message |
|---|---|---|---|---|
| m4132 | fetch | info | 2026-07-19 02:39:12.233941 | Fetch Started |
| m4132 | fetch | pass | 2026-07-19 02:39:17.416598 | Fetch complete. |
| m4132 | build | info | 2026-07-20 11:53:15.815196 | Build Started |
| m4132 | build | pass | 2026-07-20 11:55:22.182429 | Build complete. |
| m4132 | scan | info | 2026-07-21 03:29:38.860974 | Scan Started |
| m4132 | scan | info | 2026-07-21 03:29:57.796282 | Virus scan passed. |
| m4132 | scan | info | 2026-07-21 03:29:57.835609 | YARA scan passed. |
| m4132 | scan | warn | 2026-07-21 03:30:01.372837 | USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v12_0 |
| m4132 | scan | warn | 2026-07-21 03:30:01.401299 | Scan complete. |
| m4132 | test | info | 2026-07-21 19:58:46.299272 | Test Started |
| m4132 | test | pass | 2026-07-21 20:00:44.345167 | Test complete. |
scan Log
== ClamAV package scan == /mnt/magus/packages/643/iverilog-12.0_1.mport: OK == YARA port-file scan == No YARA matches. == Source integrity scan == Compared cad/iverilog between 60b86f7714364c0e1a4411b214735dc6df5c236a and c8f81094d01e568b4d50d0898787ca34889bbdb7. Changed files: cad/iverilog/Makefile cad/iverilog/distinfo cad/iverilog/pkg-descr cad/iverilog/pkg-plist Warnings: SourceIntegrityMutableGithubTag: USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v12_0
Links
Depends On
- devel/autoconf (build)
- devel/bison (build)
- devel/gmake (build)
- devel/gperf (build)
- devel/readline (build)
- devel/readline (lib)
- devel/readline (run)
Depend Of
Categories
CVEs
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