MidnightBSD Magus

cad/verilog-mode.el

Emacs lisp modules for the Verilog language

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
full 801_25 642 4.1 amd64 gpl3+ 0 warn pass pass warn

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Events

Machine Phase Type Time Message
m4164b fetch info 2026-07-06 06:14:26.544987 Fetch Started
m4164b fetch pass 2026-07-06 06:14:27.75427 Fetch complete.
m4164b build info 2026-07-19 12:19:40.639082 Build Started
m4164b build warn 2026-07-19 12:23:02.111037 MASTER_SITES contains non-HTTPS URLs: http://www.veripool.org/ftp/
m4164b build warn 2026-07-19 12:23:03.119649 Build complete.
m4164b scan info 2026-07-20 05:52:14.869827 Scan Started
m4164b scan info 2026-07-20 05:52:31.510573 Virus scan passed.
m4164b scan warn 2026-07-20 05:52:31.544912 YARA found suspicious port shell content.
m4164b scan warn 2026-07-20 05:52:31.776957 MASTER_SITES contains domain not in source allowlist: www.veripool.org
m4164b scan warn 2026-07-20 05:52:31.800712 Scan complete.
m4164b test info 2026-07-21 11:47:37.486319 Test Started
m4164b test pass 2026-07-21 11:50:47.095219 Test complete.

scan Log

== ClamAV package scan ==
/mnt/magus/packages/642/verilog-mode.el-801_25.mport: OK

== YARA port-file scan ==
/usr/mports/cad/verilog-mode.el/Makefile(1): error: syntax error, unexpected identifier
/usr/mports/cad/verilog-mode.el/Makefile(28): error: unterminated regular expression

== Source integrity scan ==
Compared cad/verilog-mode.el between 177ae033a7ad8459e5e20760b547a2b46a0c1e79 and ae7a94b0701c78a0a8609969f55d4db537ab87cf.
Changed files:
  cad/verilog-mode.el/Makefile
Warnings:
  SourceIntegrityUnknownMasterSiteDomain: MASTER_SITES contains domain not in source allowlist: www.veripool.org

Links

Depends On

Depend Of

Categories

CVEs

  • Loading CVE information...

LLM Analysis