MidnightBSD Magus

cad/surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
1.84_1 642 4.1 amd64 Apache-2.0 0 pass pass skip warn Reset Port

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Events

Machine Phase Type Time Message
m4164b fetch info 2026-07-06 06:12:01.441081 Fetch Started
m4164b fetch pass 2026-07-06 06:12:22.469687 Fetch complete.
m4164b build info 2026-07-12 02:25:08.721408 Build Started
m4164b build pass 2026-07-12 02:31:12.120327 Build complete.
m4164b scan info 2026-07-12 12:20:40.268891 Scan Started
m4164b scan fail 2026-07-12 12:20:40.297111 Virus scan found a problem.
m4164b scan internal 2026-07-12 12:20:40.329521 Exception thrown: open3: exec of yara /usr/magus/slave-data/mports/Tools/magus/yara/mports-shell.yar /usr/mports/cad/surelog/Makefile /usr/mports/cad/surelog/files/patch-CMakeLists.txt /usr/mports/cad/surelog/files/patch-include_Surelog_DesignCompile_CompileHelper.h /usr/mports/cad/surelog/files/patch-include_Surelog_Design_ModuleInstance.h /usr/mports/cad/surelog/files/patch-src_DesignCompile_CompileDesign.cpp /usr/mports/cad/surelog/files/patch-src_DesignCompile_CompileExpression.cpp /usr/mports/cad/surelog/files/patch-src_DesignCompile_ElaborationStep.cpp /usr/mports/cad/surelog/files/patch-third_party-antlr4-runtime-Cpp-CMakeLists.txt failed: No such file or directory at /usr/magus/slave-data/mports/Tools/magus/slave/../../lib/Magus/App/Slave/Worker.pm line 931.
m4164b scan info 2026-07-20 05:48:28.356835 Scan Started
m4164b scan info 2026-07-20 05:48:49.337525 Virus scan passed.
m4164b scan warn 2026-07-20 05:48:49.375013 YARA found suspicious port shell content.
m4164b scan warn 2026-07-20 05:48:54.949105 USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v1.84
m4164b scan warn 2026-07-20 05:48:54.972179 Scan complete.
m4164b test info 2026-07-21 11:18:43.58885 Test Started
m4164b test skip 2026-07-21 11:19:02.592513 surelog test phase skipped: NO_TEST is set
m4164b test skip 2026-07-21 11:19:02.670114 Test complete.

scan Log

== ClamAV package scan ==
/mnt/magus/packages/642/surelog-1.84_1.mport: OK

== YARA port-file scan ==
/usr/mports/cad/surelog/Makefile(1): error: syntax error, unexpected identifier
/usr/mports/cad/surelog/Makefile(13): error: unterminated regular expression

== Source integrity scan ==
Compared cad/surelog between 9dcdcd54a0704f4020044c7648a21e8d02f7657b and 92d400d506c2e93457e0fa5b1ce3a906faec61ef.
Changed files:
  cad/surelog/Makefile
Warnings:
  SourceIntegrityMutableGithubTag: USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v1.84

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LLM Analysis