Magus // iverilog

cad/iverilog

Verilog simulation and synthesis tool

Flavor	Version	Run	OSVersion	Arch	License	Restricted	Build	Fetch	Test	Scan
	12.0_1	641	4.0	i386	gpl2	0	pass	pass	pass	pass	Reset Port

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Machine	Phase	Type	Time	Message
m4032	fetch	info	2026-06-02 22:00:22.50001	Fetch Started
m4032	fetch	pass	2026-06-02 22:00:28.68207	Fetch complete.
m4032	build	info	2026-06-03 12:52:34.375152	Build Started
m4032	build	pass	2026-06-03 12:54:49.41783	Build complete.
m4032	scan	info	2026-06-09 06:07:40.223718	Scan Started
m4032	scan	info	2026-06-09 06:07:59.966023	Virus scan passed.
m4032	scan	pass	2026-06-09 06:07:59.973844	Scan complete.
m4032	test	info	2026-06-10 12:48:16.511202	Test Started
m4032	test	pass	2026-06-10 12:50:17.929846	Test complete.

/mnt/magus/packages/641/iverilog-12.0_1.mport: OK