cad/iverilog
Verilog simulation and synthesis tool
| Flavor | Version | Run | OSVersion | Arch | License | Restricted | Status | |
|---|---|---|---|---|---|---|---|---|
| 12.0_1 | 639 | 4.0 | amd64 | gpl2 | 0 | warn | Reset Port |
License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept
Events
| Machine | Type | Time | Message |
|---|---|---|---|
| m4064b | info | 2026-05-20 19:25:35.673493 | Test Started |
| m4064b | warn | 2026-05-20 19:27:52.646746 | fake-qa reported: /usr/local/bin/vvp is linked to /usr/local/lib/libreadline.so.8 that does not belong to any package |
| m4064b | warn | 2026-05-20 19:27:53.246671 | Test complete. |
Links
Depends On
- devel/autoconf (build)
- devel/bison (build)
- devel/gmake (build)
- devel/gperf (build)
- devel/readline (build)
- devel/readline (lib)
- devel/readline (run)
Depend Of
Categories
CVEs
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