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cad/verilator

Synthesizable Verilog to C++ compiler

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
5.026 632 4.0 amd64 gpl3 0 pass untested untested untested

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Events

Machine Phase Type Time Message
defiant info 2026-02-17 07:28:57.733994 Test Started
defiant pass 2026-02-17 07:38:00.826946 Test complete.

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