cad/iverilog
Verilog simulation and synthesis tool
| Flavor | Version | Run | OSVersion | Arch | License | Restricted | Build | Fetch | Test | Scan | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 12.0_1 | 630 | 4.0 | i386 | gpl2 | 0 | pass | untested | untested | untested |
License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept
Events
| Machine | Phase | Type | Time | Message |
|---|---|---|---|---|
| m4032 | info | 2026-02-06 16:53:26.320526 | Test Started | |
| m4032 | pass | 2026-02-06 16:55:47.899508 | Test complete. |
Links
Depends On
- devel/autoconf (build)
- devel/bison (build)
- devel/gmake (build)
- devel/gperf (build)
- devel/readline (build)
- devel/readline (lib)
- devel/readline (run)
Depend Of
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CVEs
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