cad/iverilog
Verilog simulation and synthesis tool
| Flavor | Version | Run | OSVersion | Arch | License | Restricted | Status | |
|---|---|---|---|---|---|---|---|---|
| 12.0_1 | 620 | 4.0 | amd64 | gpl2 | 0 | pass |
License Permissions:
Events
| Machine | Type | Time | Message |
|---|---|---|---|
| m4064b | info | 2025-10-29 19:04:50.123261 | Test Started |
| m4064b | pass | 2025-10-29 19:07:10.277962 | Test complete. |
Links
Depends On
- devel/autoconf (build)
- devel/bison (build)
- devel/gmake (build)
- devel/gperf (build)
- devel/readline (build)
- devel/readline (lib)
- devel/readline (run)
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